Phase locked loops (PLL) are control systems that generate signals having a fixed relation to the phase of a reference signal. Typically, a phase-locked loop circuit responds to both the frequency and the phase of input signals, raising or lowering the frequency of a controlled oscillator until an oscillator signal is matched with a reference signal in both frequency and phase. Phase-locked loops are widely used in radio, telecommunications, computers, and other electronic applications.
The use of “all-digital phase locked loops” or ADPLLs is becoming popular. An ADPLL may include the advantages of digital circuits, such as lower power consumption, flexibility, better noise immunity, capability of digital signal processing, and so on. A typical ADPLL may include a phase detector, a loop filter, and a digitally controlled oscillator (DCO).
The DCO produces a signal with a variable frequency. Generally, the input to the DCO is a digital tuning word that controls the variable output frequency. Frequency-lock is obtained by using a correct digital tuning word. However, the phases of the reference signal and the DCO output variable signal differ and have to be laboriously adapted in order to achieve phase-lock. This lengthy process contravenes the strict operating standard when hopping frequencies in Multi Band Orthogonal Frequency Division Multiplexing Ultra Wide Band (MB-OFDM-UWB).
In MB-OFDM-UWB, the PLL has to be able to produce a wide spectrum of frequencies. For example, FIG. 1 depicts five band groups. Within a single band group 102, the carrier hops between three frequency bands (104, 106 and 108). These three frequency bands (104, 106, and 108) can be separated by of 528 MHz or 1056 MHz for example.
FIG. 2 depicts a time-frequency allocation for frequency bands (104, 106, and 108). As depicted, the Y-axis represents the frequency (MHz) and the X-axis represents time. Symbol 202 corresponds to a frequency band 104 and, as time progresses, the frequency changes between each frequency band in a band group. For example, as depicted the frequency band 104 (symbol 202) hops to frequency band 106 (symbol 204), which hops to frequency band 108 (symbol 206), which hops back to frequency band 104 (symbol 208) and so forth. Each symbol (202, 204, 206 and 208) is about 312.5 nano seconds (ns), the bands being changed within, for example, a 9.5 ns hopping duration 210. Therefore, as seen in FIG. 2, a broadband frequency synthesizer has to be able to accomplish large frequency hops within an extremely short period of time (e.g. 9.5 ns). Furthermore, the time 212 between a reoccurrence of a given frequency band (e.g. 104) is also fairly short.
One conventional approach uses three PLLs, one PLL for each band within a frequency band group (i.e. FIGS. 1 104, 106 and 108). However, this requires increased space and power consumption for the transmitting or receiving device. Another conventional approach uses a single PLL in combination with mixers to generate a frequency band group. However, mixers introduce severe spurs that impair the quality of the frequency signal. Therefore, a solution with only one fast-hopping PLL (preferably an ADPLL) would have corresponding advantages. However, in order for an ADPLL to accomplish large frequency hops within an extremely short period of time (e.g. 9.5 ns); the ADPLL must be able to achieve immediate phase-lock.
Another conventional approach operates an ADPLL in an open loop mode of operation. The open loop mode of operation is eventually closed in order to calibrate a digital tuning word for a certain frequency. During transmission, the digital tuning word is continuously loaded for a given frequency band and the DCO is controlled without feedback in the open loop mode of operation. Thus, for the given frequency band, the same digital tuning word is used over and over again with no feedback in the open loop mode of operation. Moreover, the DCO is subjected to temperature variation and voltage drifting, thereby introducing an error in the output frequency signal. This conventional approach is unable to compensate for this error because it continuously operates in an open loop mode of operation. To correct for this error associated with the DCO, this approach requires waiting for transmission pauses in order to perform a calibration. Furthermore, the quality of synthesized frequencies in this approach cannot be guaranteed by the open loop mode of operation.